1. Field of the Invention
The present invention relates to a magnetic tunnel junction structure and a method of fabricating the same, and more particularly, to a magnetic tunnel junction structure having an oxidized buffer layer, and a method of fabricating the same.
2. Description of the Related Art
Semiconductor memory devices for storing information are normally classified into volatile memory devices and non-volatile memory devices. Whereas the volatile memory devices lose stored information therein when a power supply is shut off, the non-volatile memory devices still keep stored information even when a power supply is shut off. Such non-volatile memory devices including flash memory devices, ferroelectric random access memory (FeRAM) devices, and magnetic random access memory (MRAM) devices are typically used in memory cards, mobile phone communication terminals, and other electronics products in order to keep stored information therein, and to reduce power consumption.
The MRAM device includes a plurality of memory cells employing magnetic tunnel junction (MTJ) structures. The MTJ structure includes a lower magnetic layer pattern, a tunnel layer pattern and an upper magnetic layer pattern, which are stacked on a lower electrode. In accordance with the magnetization direction of the lower magnetic layer pattern and the upper magnetic layer pattern, there occurs a difference in the current amount flowing through the tunnel layer pattern. The MRAM device stores information by changing the magnetization direction or using the difference of the lower magnetic layer pattern and the upper magnetic layer pattern.
Conventionally, such an MTJ structure is fabricated by sequentially forming a lower conductive layer, a lower magnetic layer, a tunnel layer, an upper magnetic layer and an upper conductive layer on a semiconductor substrate, and then, sequentially patterning them using an photolithography and etching technique to form a lower electrode, a lower magnetic layer pattern, a tunnel layer pattern, an upper magnetic layer pattern and an upper electrode.
However, while sequentially etching the upper magnetic layer and the lower magnetic layer, etch residues may occur and cause a short circuit between the upper magnetic layer and the lower magnetic layer. Said short circuit results in a device failure in an MRAM device and must be avoided.
A method for avoiding a short circuit between the upper magnetic layer and the lower magnetic layer due to etch residues is taught by Chen et al. in U.S. Pat. No. 6,165,803 in the title of “MAGNETIC RANDOM ACCESS MEMORY AND FABRICATING METHOD THEREOF”, and taught by Signorini in U.S. Pat. No. 6,485,989 in the title of “MRAM SENSE LAYER ISOLATION”. However, the method disclosed in the U.S. Pat. No. 6,485,989 causes a reduction in etch process margin because the tunnel layer becomes thinner because the upper magnetic layer should be etched such that the etching stops on the tunnel layer.
The method disclosed in the U.S. Pat. No. 6,165,803 includes etching an upper conductive layer (or mask layer), but the etching stops on an upper magnetic layer. Then, the exposed upper magnetic layer is changed into an insulating layer as will be described below.
FIGS. 1 to 3 are cross-sectional views illustrating a method of fabricating a magnetic tunnel junction structure in accordance with the U.S. Pat. No. 6,165,803.
Referring to FIG. 1, a lower insulating layer 13 is formed on a semiconductor substrate 11. A transistor (not shown) and a digit line (not shown) are formed on the semiconductor substrate 11. The lower insulating layer 13 insulates the digit line and the magnetic tunnel junction structure. In addition, the lower insulating layer 13 has a contact hole (not shown) and a plug (not shown) to electrically connect the magnetic tunnel junction structure and the transistor.
A lower conductive layer 15, a lower magnetic layer 17, a tunnel layer 19, an upper magnetic layer 21, and an upper conductive layer 23 are sequentially formed on the lower insulating layer 13.
Referring to FIG. 2, the upper conductive layer 23, the upper magnetic layer 21, the tunnel layer 19, the lower magnetic layer 17, and the lower conductive layer 15 are sequentially patterned to form a lower electrode 15a, a lower magnetic layer pattern 17a, a tunnel layer pattern 19a, a preliminary upper magnetic layer pattern 21a and an upper conductive layer pattern, which are sequentially stacked on the lower insulating layer 13.
Next, a new mask pattern is formed on the upper conductive layer pattern. The upper conductive layer pattern is then etched using the new mask pattern as an etch mask to form an upper electrode 23a. As a result, the upper surface of the preliminary upper magnetic layer pattern 21a is exposed.
Referring to FIG. 3, the exposed portion of the preliminary upper magnetic layer pattern 21a is oxidized or nitrified to form an inactive portion 21c. As a result, a final upper magnetic layer pattern 21b is formed in a magnetic tunnel junction region, while its sidewall is surrounded by the inactive portion 21c. Next, an upper insulating layer 25 is formed on the resulting structure having the final upper magnetic layer pattern 21b, and finally a bit line 27 is formed, to be electrically connected to the upper electrode 23a. 
The method disclosed in the U.S. Pat. No. 6,165,803 decreases the likelihood of a short circuit between the final upper magnetic layer pattern 21b and the lower magnetic layer pattern 17a by using the technique of oxidizing or nitrifying the exposed portion of the preliminary upper magnetic layer pattern 21a. 
However, this technique does have some limitations. The process for oxidizing the exposed preliminary upper magnetic layer pattern 21a must be performed at a low temperature to protect the final upper magnetic layer pattern 21b in the magnetic tunnel region. Therefore, this technique results in an undesirable and restrictive temperature requirement during the oxidation process.
Further, when forming the upper electrode 23a using a photolithography and etching technique, the photoresist pattern must be removed. In the removal process, an ashing technique using an O2 plasma gas is used. However, ashing is performed at a relatively high temperature that may exceed the aforementioned temperature requirement and thus deteriorate the final upper magnetic layer pattern 21b. 
Furthermore, to meet the temperature requirement, the upper insulating layer 25 must be formed using a low temperature process, typically lower than 300° C. However, it is difficult to adequately form the upper insulating layer with a desired high density while using this low temperature process because at the low temperature the upper insulating layer has a tendency to be formed porous. As a result of a porous formation, the oxygen atoms from the O2 plasma used in the ashing technique may be diffused through the upper insulating layer 25 thus reaching and deteriorating the final upper magnetic layer pattern.
Accordingly, it is difficult to ensure process margins after the oxidation process and a subsequent ashing process required by this conventional technique. Embodiments of the invention address these and other limitations in the prior art.